ParaLarPD: Parallel FPGA Router Using Primal-Dual Sub-Gradient Method
نویسندگان
چکیده
منابع مشابه
Parallel FPGA Router using Sub-Gradient method and Steiner tree
In the FPGA (Field Programmable Gate Arrays) design flow, one of the most time-consuming step is the routing of nets. Therefore, there is a need to accelerate it. In [2], the authors have developed a Linear Programming (LP) based framework that parallelizes this routing process to achieve significant speedups (the resulting algorithm is termed as ParaLaR). However, this approach has certain wea...
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ژورنال
عنوان ژورنال: Electronics
سال: 2019
ISSN: 2079-9292
DOI: 10.3390/electronics8121439